As the use of semiconductor devices (also referred to as Integrated Circuits ((ICs) or chips) and modules, formed from a number of such devices, continues to increase, the complexity of such devices and modules is also increasing. In concert with this increased complexity is a requirement to make such devices smaller in both surface area and thickness and to make smaller modules that incorporate a plurality of such devices with this increased complexity.
It has been known for some time that to achieve the aforementioned requirement it is necessary to not only reduce surface area of such devices but to thin the device wafer from which such chips are obtained. Such thinning not only provides for dissipating heat generated by the operation of the chips, but also for enhancing their electrical performance and reducing the size of modules that incorporate such devices. Additionally, thinning can provide for the forming of through-silicon vias (TSVs) that provide electrical coupling locations on the backside of a chip thus allowing for a smaller surface area by moving front side contact areas to the chip's backside.
While there have been a number of proposed methods for thinning device wafers and performing the processing necessary to create TSVs, for the most part none of these methods have been able to provide for a laminated wafer stack that can simultaneously satisfy grinding force resistance, heat resistance during the anisotropic dry etching needed to form TSVs and chemical resistance during plating and etching, all while providing for smooth debonding of the lamination at or near room temperature.
Therefore it would be advantageous to develop materials, methods for using such materials and structures that incorporate such materials, such materials and methods including debonding a wafer from a substrate at or near room temperature while providing grinding force resistance during the back side grinding necessary for wafer thinning, heat resistance during the anisotropic dry etching needed to form TSVs and chemical resistance during plating and etching processes.